It has been found that III-N materials are a desirable semiconductor material in many electronic and photonic applications. As understood in the art, the III-N semiconductor material must be provided as a crystalline or single-crystal formation for the most efficient and useful bases for the fabrication of various electronic and photonic devices therein. Further, the single-crystal III-N semiconductor material is most conveniently formed on single-crystal silicon wafers because of the extensive background and technology developed in the silicon semiconductor industry. However, the crystal lattice constant mismatch between silicon and a III-N material, such as GaN, is 17% if grown c-axis on (111) oriented silicon.
Also, the thermal expansion difference between the III-N material, such as GaN, is 56%. Both of these factors lead to residual stress and consequently to structural defects and mechanical damage (e.g. cracks) in the structure.
A buffer layer between the silicon substrate and the III-N layer that could absorb stress would help solve the problem. Several copending patent applications have been filed in the U.S. in which rare earth oxides were grown on a silicon substrate to serve as a stress engineered buffer layer for the subsequent growth of III-N semiconductor material. Two of these copending U.S. patent applications are: Strain Compensated REO Buffer for III-N on Silicon, filed 21 Oct. 2011, bearing Ser. No. 13/278,952; and Nucleation of III-N on REO Templates, filed 20 Mar. 2012, bearing Ser. No. 61/613,289, both of which are included herein by reference.
While the rare earth oxide (REO) stress engineered buffer layers can reduce stress to a manageable level the stress can be conveniently reduced or substantially eliminated by including a layer of amorphous silicon oxide between the silicon substrate and the rare earth oxide buffer. Silicon oxide is amorphous material and has low viscosity at temperatures above 500° C. that results in stress relaxation, critical from the point of view of thermal stress during cooling down of GaN (III-N material) on silicon heterostructure. A major problem is that the formation of the amorphous silicon oxide layer must take place during the growth of the single-crystal REO buffer because growth of the REO on an amorphous silicon layer would lead to a polycrystalline REO buffer which is not suitable for single-crystal III-N growth.
There are potentially several ways to form the silicon oxide interface layer all of which have severe drawbacks. In a first method, an atmosphere of excess oxygen can be provided during the REO growth. Some problems with this method are that high oxygen pressure is needed during the process which causes the lifetime of the MBE components in the chamber to deteriorate and the SiOx layer is not thick enough to adequately perform the stress relief. In a second method, the REO is grown and the structure is subsequently annealed in oxygen atmosphere. A method of this type is described in U.S. Pat. No. 7,785,706, entitled “Semiconductor Wafer and Process for its Production”, issued Aug. 31, 2010 and U.S. Pub. 2010/0221869 of the same title. One problem with this type of method is that the formation of the interface can be hard to control, the oxidation needs long time, temperature and/or high oxygen pressure because oxidation of silicon is diffusion limited process, which means that oxidation becomes slower with increasing of thickness of the silicon dioxide layer.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide new and improved methods of forming a layer of amorphous silicon between a REO buffer and a silicon substrate.
It is another object of the present invention to provide new and improved methods of forming a layer of amorphous silicon dioxide between a REO buffer and a silicon substrate that is sufficiently thick to adequately perform stress relief that is easy and reliable to control.
It is another object of the present invention to provide a new and improved III-N semiconductor layer on a silicon substrate including a layer of amorphous silicon between a REO buffer and the substrate.